1. Field of the Invention
The present invention relates to liquid crystal displays (LCDs), and more particularly to a connector having an interface part capable of sharing multiple channels and for receiving and transmitting data in accordance with a number of channels determined by a drive system, and a driving apparatus of a liquid crystal display using the same.
2. Description of the Related Art
LCDs are advantageously small in size, thin, and consume low amounts of power and therefore are used extensively in notebook PC's, office automation equipment, audio/video equipment, etc. Active matrix LCDs (AM-LCDs) include switching devices such as TFTs and are capable of displaying moving images.
FIG. 1 illustrates a block diagram of a related art LCD.
Referring to FIG. 1, related art LCDs generally include an LCD panel 6 supporting a plurality of gate lines GL1 to GLm, a plurality of data lines DL1 to DLn crossing the plurality of gate lines, a plurality of TFTs formed at crossings of the gate and data lines for driving corresponding ones of a plurality of liquid crystal cells (Clc) defined by the crossings of the gate and data lines, a data driver 8 for applying data to the data lines DL1 to DLn, a gate driver 10 for applying scan pulses to the gate lines GL1 to GLm, a timing controller 4 for controlling the data and gate drivers 8 and 10, respectively, and an interface part 2 for applying red (R), green (G), and blue (B) digital video data (DATA) and horizontal and vertical synchronization signals (H and V, respectively) to the timing controller 4.
The LCD panel 6 generally includes an upper glass substrates bonded to, and separated from a lower glass substrate, wherein liquid crystal material is injected between the two glass substrates and wherein the plurality of gate and data lines are supported by the lower glass substrate. In response to scan pulses applied to the gate lines GL1 to GLm, the TFTs formed apply video data from the data lines DL1 to DLn to corresponding ones of the liquid crystal cells (Clc). Accordingly, each TFT includes a gate terminal connected to a gate line GL1 to GLm, a source terminal connected to a data line DL1 to DLm, and a drain terminal connected to a pixel electrode (not shown) formed in a corresponding one of the liquid crystal cells (Clc).
The gate driver 10 generally includes a shift register for sequentially generating scan pulses (i.e, gate high pulses) in response to a gate drive control signal (GDC) applied from the timing controller 4 and a level shifter for shifting the voltage of each scan pulse to an appropriate level suitable for driving the liquid crystal cells (Clc). Accordingly, the video data transmitted by the data lines DL is applied to pixel electrodes of liquid crystal cells (Clc) by the TFTs to which the scan pulses are applied.
The data driver 8 receives a data drive control signal (DDC) with digital video data (RGB) from the timing controller 4. The data driver 8 then latches the digital video data (RGB) in synchrony with the data drive control signal (DDC), corrects the latched data in accordance with a gamma voltage V generated by a gamma voltage generator (not shown), converts the corrected data into an analog data, and applies the converted analog data to the data lines DL.
The interface part 2 receives DATA and control signals such as an input clock (DCLK), a horizontal synchronization signal (H), a vertical synchronization signal (V), and a data enable signal (DE) inputted from a drive system such as a personal computer (not shown) and applies the DATA and control signals to the timing controller 4. Generally, the DATA and control signals are transmitted from the drive system to the timing controller 4 using a low voltage differential signal (LVDS) interface and a transistor-transistor logic (TTL). Interface functions can be integrated on the same chip as the timing controller 4.
FIG. 2 illustrates a block diagram of the timing controller and interface part shown in FIG. 1.
Referring to FIG. 2, the interface part 2 generally includes an LVDS transmitter 18 for transmitting various signals applied from the drive system and a first connector 12 for receiving the various signals transmitted from the LVDS transmitter 18 and for transmitting the received various signals to the timing controller 4.
The LVDS transmitter 18 generally receives the control signals and the DATA, provided as R, Q and B color signals having TTL levels applied from the drive system. In accordance with physical properties of the liquid crystal material within the LCD panel, each of the R, G, and B color signals are divided and separately applied to each LVDS transmitter 18 such that R, G, and B color signals having invertable polarities are applied to the LCD panel in accordance with a line inversion driving method or a dot inversion driving method. Further, control signals such as the horizontal synchronization signal (H), the vertical synchronization signal (V) and the data enable signal (DE) are applied to the LVDS transmitter 18. Accordingly, the LVDS transmitter 18 digitizes and compresses the input clock (DCLK), the horizontal synchronization signal (H), the vertical synchronization signal (V), and the data enable (DE) signal, to reduce voltages of the received signals down to the LVDS signal level having voltages of 1V or less. The LVDS signals are transmitted to the timing controller 4 through the first connector 12 and a second connector 14. In other words; signals applied to the LVDS transmitter 18 are converted into LVDS signals having predetermined number of channels that may then be applied to an LVDS receiver 20 built into the timing controller 4 via the first and second connectors 12 and 14, respectively.
Using the horizontal/vertical synchronization signals (H/V), the data enable (DE) signal, and the clock (CLK) outputted by the interface part 2, the timing controller 4 applies the data drive control signals DDC (e.g., a source sampling clock (SSC), a source start pulse (SSP), a source enable signal (SOE), and a polarity control signal (POL)) to the data driver 8 to thereby control the data driver 8. The timing controller 4 also applies gate drive control signals (GDC) (e.g., a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable (GOE)) to the gate driver 10 to thereby control the gate driver 10.
The timing controller 4 further re-aligns the RGB digital video data outputted by the interface part 2 and applies the re-aligned RGB digital video data to the data driver 8. Accordingly, the LVDS receiver 20 is integrated into the timing controller 4 as an application-specific integrated circuit ASIC to shield the LVDS signals applied from the second connector from electromagnetic interference while restoring the LVDS signals to their original voltage levels. Therefore, the LVDS receiver 20, supplied with the LVDS signals transmitted by the predetermined number of channels, converts the transmitted LVDS signals into a TTL signal.
FIGS. 3A and 3B illustrate the signal arrangement transmittable by pins of the first connector shown in FIG. 2.
Referring to FIG. 3A, signals transmittable by pins of the first connector 12 are confined to a single channel while, in FIG. 3B, signals transmittable by pins of the first connector 12 are confined to two channels. Accordingly, the arrangement of signals that must be transmitted by the pins of the first connector are different depending upon whether signals transmitted by the drive system are transmitted over a single channel or over a double channel. Therefore, the first connector 12 shown in FIG. 3A can only be used if a single channel is used to receive signals from the drive system whereas the first connector 12 shown in FIG. 3B is used if two channels are used to the channels receive signals from the drive system. If, however, only one channel is provided for receiving signals from the drive system but use of the first connector 12 having two channels is desired, the LCD must be disadvantageously re-designed and re-developed to incorporate an entirely new chip set and new electromagnetic shielding even though the components of the LCD panel itself remain the same.